AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
19
9634E–AT42–06/12
AT42QT2120
31 Key 3 Control Reserved GUARD AKS GPO EN R/W
32 Key 4 Control
Reserved GUARD AKS GPO EN R/W
33 Key 5 Control
Reserved GUARD AKS GPO EN R/W
34 Key 6 Control
Reserved GUARD AKS GPO EN R/W
35 Key 7 Control
Reserved GUARD AKS GPO EN R/W
36 Key 8 Control Reserved GUARD AKS GPO EN R/W
37 Key 9 Control
Reserved GUARD AKS GPO EN R/W
38 Key 10 Control
Reserved GUARD AKS GPO EN R/W
39 Key 11 Control Reserved GUARD AKS GPO EN R/W
40 Key 0 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
41 Key 1 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
42 Key 2 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
43 Key 3 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
44 Key 4 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
45 Key 5 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
46 Key 6 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
47 Key 7 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
48 Key 8 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
49 Key 9 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
50 Key 10 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
51 Key 11 Pulse Scale PULSE3 PULSE2 PULSE1 PULSE0 SCALE3 SCALE2 SCALE1 SCALE0 R/W
52–53 Key Signal 0 Key signal 0 (MSByte) – Key signal 0 (LSByte) R
54–55 Key Signal 1 Key signal 1 (MSByte) – Key signal 1 (LSByte) R
56–57 Key Signal 2 Key signal 2 (MSByte) – Key signal 2 (LSByte) R
58–59 Key Signal 3 Key signal 3 (MSByte) – Key signal 3 (LSByte) R
60–61 Key Signal 4 Key signal 4 (MSByte) – Key signal 4 (LSByte) R
62–63 Key Signal 5 Key signal 5 (MSByte) – Key signal 5 (LSByte) R
64–65 Key Signal 6 Key signal 6 (MSByte) – Key signal 6 (LSByte) R
66–67 Key Signal 7 Key signal 7 (MSByte) – Key signal 7 (LSByte) R
68–69 Key Signal 8 Key signal 8 (MSByte) – Key signal 8 (LSByte) R
70–71 Key Signal 9 Key signal 9 (MSByte) – Key signal 9 (LSByte) R
72–73 Key Signal 10 Key signal 10 (MSByte) – Key signal 10 (LSByte) R
74–75 Key Signal 11 Key signal 11 (MSByte) – Key signal 11 (LSByte) R
76–77 Reference Data 0 Reference data 0 (MSByte) – Reference data 0 (LSByte) R
78–79 Reference Data 1 Reference data 1 (MSByte) – Reference data 1 (LSByte) R
80–81 Reference Data 2 Reference data 2 (MSByte) – Reference data 2 (LSByte) R
82–83 Reference Data 3 Reference data 3 (MSByte) – Reference data 3 (LSByte) R
84–85 Reference Data 4 Reference data 4 (MSByte) – Reference data 4 (LSByte) R
Table 5-1. Internal Register Address Allocation (Continued)
Address Use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W