AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
17
9634E–AT42–06/12
AT42QT2120
Note: Reading the 16-bit reference and signal values is not an automatic operation; reading
the first byte of a 16-bit value does not lock the other byte. As a result glitches in the
reported value may be seen as values increase from 255 to 256, or decrease from 256
to 255. This device also supports the use of a repeated START condition as an
alternative to the Stop condition.
4.4 SDA, SCL
The I
2
C-compatible bus transmits data and clock with SDA and SCL respectively. They are
open-drain; that is I
2
C-compatible master and slave devices can only drive these lines low or
leave them open. The termination resistors pull the line up to Vdd if no I
2
C-compatible device is
pulling it down.
The termination resistors commonly range from 1 k to 10 k
and should be chosen so that the
rise times on SDA and SCL meet the I
2
C-compatible specifications (300 ns maximum for
400 kHz operation).
4.5 Standalone Mode
If I
2
C-compatible communications are not required, then standalone mode can be enabled by
connecting the MODE pin to Vdd. See Section 2.4 on page 9 for more information.
In Standalone mode (Mode pin connected to Vdd at start-up) the chip is configured to specific
settings:
• Key0 is configured as a proximity channel. If this key goes into detect then PXOUT is
asserted high.
• Key1 is configured as a guard channel and should have a PCB layout which reflects this.
• Keys 2 – 6 are standard QTouchADC keys and have pins OUT 2 – 6 configured to reflect
their respective touch status.
• Keys1 – 6 are configured to have the same AKS group setting.