AT42QT2120 Datasheet

15
9634E–AT42–06/12
AT42QT2120
4. I
2
C-compatible Communications (Comms Mode Only)
4.1 I
2
C-compatible Protocol
4.1.1 Protocol
The I
2
C-compatible protocol is based around access to an address table (see Table5-1 on
page18) and supports multibyte reads and writes. The maximum clock rate is 400 kHz.
See Section A on page 41 for an overview of I
2
C bus operation.
4.1.2 Signals
The I
2
C-compatible interface requires two signals to operate:
• SDA – Serial Data
• SCL – Serial Clock
A third line, CHANGE
, is used to signal when the device has seen a change in the status byte:
• CHANGE
: Open-drain, active low when the device status has changed since the last I
2
C
read. After reading the four status bytes
(1)
(or all the status bytes which have changed since
the previous read), this pin floats (high) again if it is pulled up with an external resistor. If the
status bytes change back to their original state before the host has read the status bytes (for
example, a touch followed by a release), the CHANGE
line is held low. In this case, a read to
any memory location clears the CHANGE
line.
4.2 I
2
C-compatible Address
There is one preset I
2
C-compatible address of 0x1C (28). This is not changeable.
4.3 Data Read/Write
4.3.1 Address Pointer
The internal address pointer is initialized to address 0.
4.3.2 Writing Data to the Device
The sequence of events required to write data to the device is shown next.
1. Detection Status Byte, Key Status Byte[0], Key Status Byte[1], Slider Position
Table 4-1. Description of Write Data Bits
Key Description
S START condition
SLA+W Slave address plus write bit
A Acknowledge bit
MemAddress Target memory address within device
Data Data to be written
P Stop condition
SLA+W
MemAddress
AAS
Data A
P
Host to Device Device Tx to Host