AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
10
9634E–AT42–06/12
AT42QT2120
2.6 Adjacent Key Suppression (AKS) Technology
The device includes the Atmel patented Adjacent Key Suppression (AKS) technology, to allow
the use of tightly spaced keys on a keypad with no loss of selectability by the user.
There can be up to three AKS groups, implemented so that only one key in the group may be
reported as being touched at any one time. Once a key in a particular AKS group is in detect no
other key in that group can go into detect. Only when the key in detect goes out of detection can
another key go into detect state.
Keys which are members of the AKS groups can be set in the Key Control register (see
Section 5.17 on page 26). Keys outside the group may be in detect simultaneously.
Note: To use a key as a guard channel, its AKS group should be set to be the same as that of
the keys it is to protect.
2.7 CHANGE Line (Comms Mode Only)
The CHANGE line is active low and signals when there is a change of state in the Detection
Status and/or Key Status bytes. It is cleared (allowed to float high) when the host reads the
status bytes.
If the status bytes change back to their original state before the host has read the status bytes
(for example, a touch followed by a release), the CHANGE
line will be held low. In this case, a
read to any memory location will clear the CHANGE
line.
The CHANGE
line is open-drain and should be connected via a 47 k resistor to Vdd. It is
necessary for minimum power operation as it ensures that the QT2120 can sleep for as long as
possible. Communications wake up the QT2120 from sleep causing a higher power
consumption if the part is randomly polled.
Note that the CHANGE
line is pulled low 85 ms after power-up or reset. The CHANGE line is
pulled low approximately for another 16 ms before any bursting on the touch pins will occur. If
any of the pins are required to be outputs then the relevant Key Control settings should be
written within this 16 ms time to prevent bursting on pins required as outputs. Also note that the
CHANGE
line is cleared during a read of the Detection Status bytes when all bytes differing from
the previous read have been read.
2.8 Types of Reset
2.8.1 External Reset
An external reset logic line can be used if desired, fed into the RESET
pin. However, under most
conditions it is acceptable to tie RESET
to Vdd. The minimum reset pulse width is 2 µs.
2.8.2 Soft Reset
The host can cause a device reset by writing a nonzero value to the Reset byte. This soft reset
triggers the internal watchdog timer on a 125 ms interval. After 125 ms the device executes a full
reset.
The device NACKs any attempts to communicate with it for approximately 200 ms after the soft
reset command. Communication can begin as soon the CHANGE
line is first asserted.
Note: The device can process a Soft Reset command while in Power Down (LPM = 0) mode,
causing a chip reset.