bmp280 datasheet
Table Of Contents
- 1. Specification
- 2. Absolute maximum ratings
- 3. Functional description
- 4. Global memory map and register description
- 5. Digital interfaces
- 6. Pin-out and connection diagram
- 7. Package, reel and environment
- 8. Appendix 1: Computation formulae for 32 bit systems
- 9. Legal disclaimer
- 10. Document history and modification
Bosch
Sensortec | BMP280 Data sheet
27 |
48
Modifications reserved | Data subject to change without notice
Document number: BST-BMP280-DS001-23 Revision_1.23_11202
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4.3.7 Register 0xFA…0xFC “temp” (_msb, _lsb, _xlsb)
The “temp” register contains the raw temperature measurement output data ut[19:0]. For details on
how to read out the pressure and temperature information from the device, please consult chapter 3.9.
Table 25: Register 0xFA … 0xFC “temp”
Register 0xFA-
0xFC “ press”
Name
Description
0xFA
temp_msb[7:0]
Contains the MSB part ut[19:12] of the raw
temperature measurement output data.
0xFB temp_lsb[7:0] Contains the LSB part ut[11:4] of the raw
temperature measurement output data.
0xFC (bit 7, 6, 5, 4)
temp_xlsb[3:0]
Contains the XLSB part ut[3:0] of the raw
temperature measurement output data. Contents
depend on pressure resolution, see Table 4.
5. Digital interfaces
The BMP280 supports the I²C and SPI digital interfaces; it acts as a slave for both protocols. The I²C
interface supports the Standard, Fast and High Speed modes. The SPI interface supports both SPI
mode ‘00’ (CPOL = CPHA = ‘0’) and mode ‘11’ (CPOL = CPHA = ‘1’) in 4-wire and 3-wire configuration.
The following transactions are supported:
• Single byte write
• multiple byte write (using pairs of register addresses and register data)
• single byte read
• multiple byte read (using a single register address which is auto-incremented)
5.1 Interface selection
Interface selection is done automatically based on CSB (chip select) status. If CSB is connected to
V
DDIO
, the I²C interface is active. If CSB is pulled down, the SPI interface is activated. After CSB has
been pulled down once (regardless of whether any clock cycle occurred), the I²C interface is disabled
until the next power-on-reset. This is done in order to avoid inadvertently decoding SPI traffic to
another slave as I²C data. Since power-on-reset is only executed when both V
DD
and V
DDIO
are
established, there is no risk of incorrect protocol detection due to power-up sequence used. However,
if I²C is to be used and CSB is not directly connected to V
DDIO
but rather through a programmable pin,
it must be ensured that this pin already outputs the V
DDIO
level during power-on-reset of the device. If
this is not the case, the device will be locked in SPI mode and not respond to I²C commands.
5.2 I²C Interface
The I²C slave interface is compatible with Philips I²C Specification version 2.1. For detailed timings
refer to Table 27. All modes (standard, fast, high speed) are supported. SDA and SCL are not pure
open-drain. Both pads contain ESD protection diodes to VDDIO and GND. As the devices does not
perform clock stretching, the SCL structure is a high-Z input without drain capability.










