pca9306 datasheet

200 kŸ
R
PU
R
PU
R
PU
R
PU
V
REF2
V
REF1
V
CC1
= +1.8 V
V
gs
+
-
V
CC2
= +3.3 V
SDA2
SCL1
SDA1
SCL2
V
CC1
< V
CC2
Normal Setup
+1.8 V + V
TH
I
REF2
= 4 µA
EN
9
PCA9306
www.ti.com SCPS113M –OCTOBER 2004–REVISED APRIL 2019
Product Folder Links: PCA9306
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8 Detailed Description
8.1 Overview
The PCA9306 device is a dual bidirectional I
2
C and SMBus voltage-level translator with an enable (EN) input and
operates without use of a direction pin. The voltage supply range for V
REF1
is 1.2 V to 3.3 V and the supply range
for V
REF2
is 1.8 V to 5.5 V.
The PCA9306 device can also be used to run two buses, one at 400-kHz operating frequency and the other at
100-kHz operating frequency. If the two buses are operating at different frequencies, the 100-kHz bus must be
disconnected by using the EN pin when the 400-kHz operation of the main bus is required. If the master is
running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because of the delays
added by the level shifter.
In I
2
C applications, the bus capacitance limit of 400 pF restricts the number of devices and bus length. The
capacitive load on both sides of the PCA9306 device must be taken into account when approximating the total
load of the system, ensuring the sum of both sides is under 400 pF.
Both the SDA and SCL channels of the PCA9306 device have the same electrical characteristics, and there is
minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete-
transistor voltage-translation solutions, because the fabrication of the switch is symmetrical. The translator
provides excellent ESD protection to lower-voltage devices and at the same time protects less-ESD-resistant
devices.
8.1.1 Definition of threshold voltage
This document references a threshold voltage denoted as V
th
, which appears multiple times throughout this
document when discussing the NFET between V
REF1
and V
REF2
. The value of V
th
is approximately 0.6 V at room
temperature.
8.1.2 Correct Device Set Up
In a normal set up shown in Figure 6, the enable pin and V
REF2
are shorted together and tied to a 200-kΩ
resistor, and a reference voltage equal to V
REF1
plus the FET threshold voltage is established. This reference
voltage is used to help pass lows from one side to another more effectively while still separating the different pull
up voltages on both sides.
Figure 6. Normal Setup