pca9306 datasheet
Table Of Contents
- 1 Features
- 2 Applications
- 3 Description
- Table of Contents
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Switching Characteristics AC Performance (Translating Down) (EN = 3.3 V)
- 6.7 Switching Characteristics AC Performance (Translating Down) (EN = 2.5 V)
- 6.8 Switching Characteristics AC Performance (Translating Up) (EN = 3.3 V)
- 6.9 Switching Characteristics AC Performance (Translating Up) (EN = 2.5 V)
- 6.10 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 8.1 Overview
- 8.1.1 Definition of threshold voltage
- 8.1.2 Correct Device Set Up
- 8.1.3 Disconnecting a Slave from the Main I2C Bus Using the EN Pin
- 8.1.4 Supporting Remote Board Insertion to Backplane with PCA9306
- 8.1.5 Switch Configuration
- 8.1.6 Master on Side 1 or Side 2 of Device
- 8.1.7 LDO and PCA9306 Concerns
- 8.1.8 Current Limiting Resistance on VREF2
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.1 Overview
- 9 Application and Implementation
- 10 Power Supply Recommendations
- 11 Layout
- 12 Device and Documentation Support
- 13 Mechanical, Packaging, and Orderable Information
V
gs
+
-
V
REF1
V
REF2
PCA9306
V
CC1
< V
CC2
EN
200 kŸ
V
CC2
= +3.3 V
Ven = Vref1 + V
TH
LDO
V
out
= +1.8 V
C
REF1
Ibias = (Vcc2 ±Ven) / 200 k
Rpulldown
Translator Setup
V
gs
+
-
V
REF1
pin
V
REF2
pin
PCA9306
V
CC1
< V
CC2
EN
200 kŸ
V
CC2
= +3.3 V
Ven = Vref1 + V
TH
V
REF1
= Vcc2 - Vth
+
-
LDO
V
out
C
REF1
Ibias = (Vcc2 ±Ven) / 200 k
Translator Setup with Vref1
provided by LDO and no path
for bias current
13
PCA9306
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SCPS113M –OCTOBER 2004–REVISED APRIL 2019
Product Folder Links: PCA9306
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Overview (continued)
8.1.7 LDO and PCA9306 Concerns
The V
REF1
pin can be supplied by a low-dropout regulator (LDO), but in some cases the LDO may lose its
regulation because of the bias current from V
REF2
to V
REF1
. If the LDO cannot sink the bias current, then the
current has no other paths to ground and instead charges up the capacitance on the V
REF1
node (both external
and parasitic). This results in an increase in voltage on the V
REF1
node. If no other paths for current to flow are
established (such as back biasing of body diodes or clamping diodes through other devices on the V
REF1
node),
then the V
REF1
voltage ends up stabilizing when V
gs
of the pass FET is equal to V
th
. This means V
REF1
node
voltage is V
CC2
- V
th
. Note that any slaves/masters running off of the LDO now see the V
CC2
- V
th
voltage which
may cause damage to those slaves/masters if they are not rated to handle the increased voltage.
Figure 13. Example of no leakage current path when using LDO
To ensure LDO does not lose regulation due to the bias current of PCA9306, a weak pull down resistor can be
placed on V
REF1
to ground to provide a path for the bias current to travel. The recommended pull down resistor is
calculated by Equation 4 where 0.75 gives about 25% margin for error incase bias current increases during
operation.
Figure 14. Example with Leakage current path when using an LDO
V
en
= V
REF1
+ V
th
where
• V
th
is approximately 0.6 V (1)
I
bias
= (V
CC2
- V
en
)/200k (2)
R
pulldown
= V
OUT
/I
bias
(3)
Recommended R
pulldown
= R
pulldown
x 0.75 (4)