pca9306 datasheet

3.3 V I
2
C bus
(1 MHz)
PCA9306
3.3 V I
2
C bus
(400 kHz)
EN
GPIO
Note: GPIO logic high must not
exceed 3.3 V +Vth in this example
200k Ÿ
R
PU
R
PU
R
PU
R
PU
V
REF2
V
REF1
V
CC1
= +1.8 V
V
gs
+
-
V
CC2
= +3.3 V
SDA2
SCL1
SDA1
SCL2
V
CC1
< V
CC2
Abnormal Setup
EN
10
PCA9306
SCPS113M –OCTOBER 2004–REVISED APRIL 2019 www.ti.com
Product Folder Links: PCA9306
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Overview (continued)
Care should be taken to ensure V
REF2
has an external resistor tied between it and V
CC2
. If V
REF2
is tied directly to
the V
CC2
rail without a resistor, then there is no external resistance from the V
CC2
to V
CC1
to limit the current such
as in Figure 7. This effectively looks like a low impedance path for current to travel through and potentially break
the pass FET if the current flowing through the pass FET is larger than the absolute maximum continuous
channel current specified in section 6.1. The continuous channel current is larger with a higher voltage difference
between V
CC1
and V
CC2
.
Figure 7 shows an improper set up. If V
CC2
is larger than V
CC1
but less than V
th
, the impedance between V
CC1
and V
CC2
is high resulting in a low drain to source current, which does not cause damage to the device. Concern
arises when V
CC2
becomes larger than V
CC1
by V
th
. During this event, the NFET turns on and begin to conduct
current. This current is dependent on the gate to source voltage and drain to source voltage.
Figure 7. Abnormal Setup
8.1.3 Disconnecting a Slave from the Main I2C Bus Using the EN Pin
PCA9306 can be used as a switch to disconnect one side of the device from the main I2C bus. This can be
advantageous in multiple situations. One instance of this situation is if there are devices on the I2C bus which
only supports fast mode (400 kHz) while other devices on the bus support fast mode plus (1 MHz). An example
of this is displayed in Figure 8.
Figure 8. Example of an I2C bus with multiple supported frequencies
In this situation, if the master is on the 1 MHz side then communicating at 1 MHz should not be attempted if
PCA9306 were enabled. It needs to be disabled for PCA9306 to avoid possibly glitching state machines in
devices which were designed to operate correctly at 400 kHz or slower. When PCA9306 is disabled, the master
can communicate with the 1 MHz devices without disturbing the 400 kHz bus. When the PCA9306 is enabled,
communication across both sides at 400 kHz is acceptable.