pca9539 datasheet

1 2 3 4 5 6 7 8 9
S 1 1 1 0 1 A1 A0 1 A 7 6 5 4 3 2 1 0 A
I0.x
7 6 5 4 3 2 1 0 A
I1.x
7 6 5 4 3 2 1 0 A
I0.x
7 6 5 4 3 2 1 0 1
I1.x
P
R/W
SCL
SDA
INT
t
ir
t
iv
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
Acknowledge
From Master
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
No Acknowledge
From Master
1 0 1 A1 A01 11 0 1 A1 A01 1S 0 A A A
R/W
A
PNA
S
R/W
1 MSB LSB
MSB LSB
Slave Address
Acknowledge
From Slave
Command Byte
Data From Upper
or Lower Byte
of Register
Last Byte
Data
Acknowledge
From Slave
Acknowledge
From Slave
Slave Address
Data From Lower
or Upper Byte
of Register
First Byte
Data
No Acknowledge
From Master
Acknowledge
From Master
At this moment, master
transmitter becomes master
receiver, and slave receiver
becomes slave transmitter.
PCA9539
SCPS130G –AUGUST 2005–REVISED JUNE 2014 www.ti.com
Figure 26. Read From Register
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 26 for these details).
Figure 27. Read Input Port Register, Scenario 1
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