sx150x_89b-datasheet

ADVANCED COMMUNICATIONS & SENSING
Rev 4 – 26
th
April 2011 9 www.semtech.com
SX1508B/SX1509B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
Symbol Description Conditions Min Typ Max Unit
f
SCL
SCL clock frequency - - - 400
kHz
t
HD;STA
Hold time (repeated) START
condition
- 0.6 - - µs
t
LOW
LOW period of the SCL clock - 1.3 - - µs
t
HIGH
HIGH period of the SCL clock - 0.6 - - µs
t
SU;STA
Set-up time for a repeated
START condition
- 0.6 - - µs
t
HD;DAT
Data hold time - 0
(4)
- 0.9
(5)
µs
t
SU;DAT
Data set-up time - 100
(6)
- - ns
t
r
Rise time of both SDA and SCL -
20+0.1C
b
(7
)
- 300 ns
t
f
Fall time of both SDA and SCL -
20+0.1C
b
(7
)
- 300 ns
t
SU;STO
Set-up time for STOP condition - 0.6 - - µs
t
BUF
Bus free time between a STOP
and START condition
- 1.3 - - µs
C
b
Capacitive load for each bus line - - - 400 pF
V
nL
Noise margin at the LOW level
for each connected device
(including hysteresis)
- -
0.1*
VDDM
- V
V
nH
Noise margin at the HIGH level
for each connected device
(including hysteresis)
- -
0.2*
VDDM
- V
t
SP
Pulse width of spikes
suppressed by the input filter
- - - 50 ns
Miscellaneous
RPULL
Programmable pull-up/down
resistors for IO[0-7]
- - 42 - k
Ω
Internal 1.3 2 2.6
f
OSC
Oscillator frequency
External from OSCIN
(40-60% duty cycle)
- - 2.6
MHz
(1) Assuming no load connected to outputs and inputs fixed to VCC1,2 or GND.
(2) Can be increased by tying together and driving simultaneously several I/Os.
(3) All values referred to VIH
MR min
and VIL
M max
levels.
(4) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to VIH
MR min
) to bridge the undefined region of
the falling edge of SCL.
(5) The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
(6) A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement t
SU;DAT
≥ 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
r max
+ t
SU;DAT
= 1000 + 250
= 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.
(7) C
b
= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.
(8) With RegHighInput bit enabled (VCCx min =1.65V), else 3.6V (VCCx min = 1.2V)
Table 5 – Electrical Specifications