sx150x_89b-datasheet

ADVANCED COMMUNICATIONS & SENSING

Rev 4 – 26

April 2011 13 www.semtech.com

SX1508B/SX1509B

World’s Lowest Voltage Level Shifting GPIO

with LED Driver and Keypad Engine

The SX1508B and SX1509B are read-write slave-mode I

C devices and comply with the Philips I

C standard

Version 2.1 dated January, 2000. The SX1508B and SX1509B have a few user-accessible internal 8-bits

registers to set the various parameters of operation (Cf. §5 for detailed configuration registers description). The

C interface has been designed for program flexibility, in that once the slave address has been sent to the

SX1508B or SX1509B enabling it to be a slave transmitter/receiver, any register can be written or read

independently of each other. The start and stop commands frame the data-packet and the repeat start condition

is allowed if necessary.

Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by

the SX1508B and SX1509B. The SX1508B and SX1509B are not CBUS compatible and can operate in standard

mode (100kbit/s) or fast mode (400kbit/s).

4.4.1 WRITE

After the start condition [S], the slave address (SA) is sent, followed by an eighth bit (‘0’) indicating a Write. The

slave then Acknowledges [A] that it is being addressed, and the Master sends an 8 bit Data Byte consisting of

the slave Register Address (RA). The Slave Acknowledges [A] and the master sends the appropriate 8 bit Data

Byte (WD0). Again the slave Acknowledges [A]. In case the master needs to write more data, a succeeding 8 bit

Data Byte will follow (WD1), acknowledged by the slave [A]. This sequence will be repeated until the master

terminates the transfer with the Stop condition [P].

Figure 7 - 2-Wire Serial Interface, Write Operation

When successive register data (WD1...WDn) is supplied by the master, the register address can be

automatically incremented or kept fixed depending on the setting programmed in RegMisc.

Figure 8 – Example: Write RegData Register

4.4.2 READ

After the start condition [S], the slave address (SA) is sent, followed by an eighth bit (‘0’) indicating a Write. The

slave then Acknowledges [A] that it is being addressed, and the Master responds with an 8 bit Data consisting of

the Register Address (RA). The slave Acknowledges [A] and the master sends the Repeated Start Condition

[Sr]. Once again, the slave address (SA) is sent, followed by an eighth bit (‘1’) indicating a Read.

The slave responds with an Acknowledge [A] and the read Data byte (RD0). If the master needs to read more

data it will acknowledge [A] and the slave will send the next read byte (RD1). This sequence can be repeated

until the master terminates with a NACK [N] followed by a stop [P].