Datasheet

SM646UDR26485-2-I
January 31, 2006
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22
Parameter Symbol
3.0ns @ CL 5.0
DDR2-667
Unit Notes
Min Max
Clock cycle time CL=5.0 t
CK
3000 8000 ps 12, 20
CL=4.0 3750 8000 ps 12, 20
CL=3.0 5000 8000 ps 12, 20
Clock high-level width t
CH
0.45 0.55 t
CK
14
Clock low-level width t
CL
0.45 0.55 t
CK
14
Clock half period t
HP
Min
(t
CL
, t
CH
)
-ps15
DQ output access time from CK/CK# t
AC
-450 +450 ps
Data-out high-impedence window from CK/CK# t
HZ
-t
AC
(max) ps 4, 5
Data-out low-impedence window from CK/CK# t
LZ
t
AC
(min) t
AC
(max) ps 4, 6
DQ & DM input setup time relative to DQS t
DS
100 - ps 3, 11, 17
DQ & DM input hold time relative to DQS t
DH
175 - ps 3, 11, 17
DQ & DM input pulse width (for each input) t
DIPW
0.35 - t
CK
Data hold skew factor t
QHS
- 340 ps
DQ-DQS hold, DQS to first DQ to go nonvalid, per
access
t
QH
t
HP
- t
QHS
- ps 11,13
DQS input high pulse width t
DQSH
0.35 - t
CK
DQS input low pulse width t
DQSL
0.35 - t
CK
DQS output access time from CK/CK# t
DQSCK
-400 +400 ps
DQS falling edge to CK rising - setup time t
DSS
0.2 - t
CK
DQS falling edge from CK rising - hold time t
DSH
0.2 - t
CK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
t
DQSQ
- 240 ps 11,13
DQS read preamble t
RPRE
0.9 1.1 t
CK
18
DQS read postamble t
RPST
0.4 0.6 t
CK
DQS write preamble setup time t
WPRES
0 - ps 8, 9
DQS write preamble t
WPRE
0.35 - t
CK
DQS write postamble t
WPST
0.4 0.6 t
CK
7
Write command to first DQS latching transition t
DQSS
WL - 0.25 WL + 0.25 t
CK
Address & control input pulse width for each input t
IPW
0.6 - t
CK
Address and control input setup time t
IS
200 - ps 2, 17
Address and control input hold time t
IH
275 - ps 2, 17
CAS# to CAS# command delay t
CCD
2- t
CK
OCD Drive mode delay t
OIT
012ns
Device AC Operating Conditions