Datasheet

SM646UDR26485-2-I
January 31, 2006
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21
IDD Testing Parameters
DDR2-667
Parameter 5-5-5 Units
CL(IDD) 5 t
CK
t
RCD(IDD)
15 ns
t
RC(IDD)
60 ns
t
RRD(IDD)
7.5 ns
t
CK(IDD)
3ns
t
RASmin(IDD)
45 ns
t
RASmax(IDD)
70000 ns
t
RP(IDD)
15 ns
t
RFC(IDD)
105 ns
IDD Specification Parameters and Test Conditions (Contd.)
Notes:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Parametric Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#. IDD values must be met with all combinations of ERMS bits 10 and
11.
5. Definitions for IDD
LOW = V
in
≤ V
IL(AC)
(max)
HIGH = V
in
≥ V
IH(AC)
(min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at V
REF
= V
DDQ
/2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for
address and control signals, and inputs between HIGH and LOW every other data transfer
(once per clock) for DQ signals not including masks of strobes.