Datasheet

SM646UDR26485-2-I
January 31, 2006
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20
IDD Specification Parameters and Test Conditions
(V
DD
= 1.8V±0.1V, V
SS
= 0V, T
A
= 0 to +65°C)
Symbol Parameter
3.0ns
CL 5.0
Unit
IDD0 Operating one bank active–precharge current; t
CK
= t
CK(IDD),
t
RC
= t
RC(IDD),
t
RAS
=
t
RASmin(IDD)
; CKE and CS# are HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
570 mA
IDD1 Operating one bank active–read–precharge current; I
OUT
= 0mA; BL = 4, CL = CL(IDD),
AL = 0; t
CK
= t
CK(IDD),
t
RC
= t
RC(IDD),
t
RAS
= t
RASmin(IDD),
t
RCD
= t
RCD(IDD)
; CKE and
CS# are HIGH between valid commands; Address bus inputs are SWITCHING; Data pat-
tern is same as IDD4W
680 mA
IDD2P Precharge power–down current; All banks idle; t
CK
= t
CK(IDD);
CKE is LOW; Other con-
trol and address bus inputs are STABLE; Data bus inputs are FLOATING
40 mA
IDD2Q Precharge quiet standby current; All banks idle; t
CK
= t
CK(IDD);
CKE is HIGH, CS# is
HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
320 mA
IDD2N Precharge standby current; All banks idle; t
CK
= t
CK(IDD);
CKE is HIGH, CS# is HIGH;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
400 mA
IDD3P Active power–down current; All banks open; t
CK
= t
CK(IDD);
CKE is
LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Fast PDN Exit
MRS(12) = 0
150 mA
Slow PDN Exit
MRS(12) = 1
50 mA
IDD3N Active standby current; All banks open; t
CK
= t
CK(IDD),
t
RAS
= t
RASmax(IDD),
t
RP
=
t
RP(IDD)
; CKE is HIGH, CS# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
400 mA
IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL =
CL(IDD), AL = 0; t
CK
= t
CK(IDD),
t
RAS
= t
RASmax(IDD),
t
RP
= t
RP(IDD)
; CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
1120 m A
IDD4R Operating burst read current; All banks open, Continuous burst reads, I
OUT
= 0mA; BL =
4, CL = CL(IDD), AL = 0; t
CK
= t
CK(IDD),
t
RAS
= t
RASmax(IDD),
t
RP
= t
RP(IDD)
; CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
pattern is same as IDD4W
1040 mA
IDD5B Burst refresh current; t
CK
= t
CK(IDD)
; Refresh command at every t
RFC(IDD)
interval; CKE
is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
1120 m A
IDD6 Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
40 mA
IDD7 Operating bank interleave read current; All bank interleaving reads, I
OUT
= 0mA; BL = 4,
CL = CL(IDD), AL = t
RCD(IDD)
-1*t
CK(IDD)
; t
CK
= t
CK(IDD),
t
RC
= t
RC(IDD),
t
RRD
= t
RRD(IDD),
t
RCD
= 1*t
CK(IDD)
; CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are STABLE during DESELECTs; Data pattern is same as IDD4R
1180 m A