Datasheet

SM646UDR26485-2-I
January 31, 2006
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19
OCD Default Output Characteristics
(V
DD
= 1.8V±0.1V, V
SS
= 0V, T
A
= 0 to +65°C)
Notes:
1. Absolute specifications: 0°C ≤ T
case
≤ +85°C; V
DDQ
= +1.8V±0.1V, V
DD
= +1.8V±0.1V.
2. Impedance measurement condition for output source DC current: V
DDQ
= 1.7V; V
OUT
= 1420mV; (V
OUT
-
V
DDQ
)/I
OH
must be less than 23.4Ω for values of V
OUT
between V
DDQ
and V
DDQ
- 280mV. Impedance mea-
surement condition for output sink DC current: V
DDQ
= 1.7V; V
OUT
= 280mV; V
OUT
/I
OL
must be less than
23.4Ω for values of V
OUT
between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and volt-
age.
4. Output slew rate for falling and rising edges is measured between V
TT
- 250mV and V
TT
+ 250mV for single
ended signals. For differential signals output slew rate is measured between DQS - DQS# = -500mV and
DQS# - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each
device.
5. The absolute value of the slew rate as measured from V
IL
(DC) max to V
IH
(DC) min is equal to or greater than
the slew rate as measured from V
IL
(AC) max to V
IH
(AC) min. This is guaranteed by design and characteriza-
tion.
6. This represents the step size when the OCD is near 18Ω at nominal conditions across all process and repre-
sent only the DRAM uncertainty.
7. Timing skew due to DRAM output slew rate mis-match between DQS/DQS# and associated DQs is included in
t
DQSQ
and t
QHS
specification.
Parameter Symbol Min Nom Max Unit Notes
Output Impedance 12.6 18 23.4 Ω 1, 2
Pull-up and Pull-down mismatch 0 4 Ω 1, 2, 3
Output Slew Rate S
OUT
1.5 5 V/ns 1, 4, 5, 7
Output Step Size for Calibration 0 1.5 Ω 6
Output Slew Rate Load Diagram
Reference Point
V
TT
Output
(V
OUT
)
25Ω