Datasheet

SM646UDR26485-2-I
January 31, 2006
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15
Commands
The following Truth Tables provide a general reference of available commands. For a more detailed description please refer to
the device data sheets.
Truth Table - Commands
Notes:
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock.
2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted.
4. The Power Down Mode does not perform any refresh operations. The duration of power down is therefore limited by the refresh require-
ments.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. “X” means “H or L (but a defined logic level)”.
7. Self Refresh Exit is asynchronous.
8. An = A12 for 256Mb, A13 for 512Mb & 1 Gb, A14 for 2Gb.
9. BAn = BA1 for upto 512Mb , BA2 for 1 Gb & 2Gb.
Function
CKE
CS# RAS# CAS# WE#
BA0~
BAn
9
An
8
~A11
A10 A9~A0 Notes
Previous
cycle
Current
cycle
(Extended) Mode Register Set H H LLLLBA OP Code 1, 2
Refresh H H LLLHX X X X1
Self Refresh Entry H L L L L H X X X X 1
Self Refresh Exit L H
HXXX
XXXX1, 7
LHHH
Single Bank Precharge H H L L H L BA X L X 1, 2
Precharge All Banks H H L L H L X X H X 1
Bank Activate H H L L H H BA Row Address 1, 2
Write H H L H L L BA Column L Column 1, 2, 3
Write with Auto-Precharge H H L H L L BA Column H Column 1, 2, 3
Read H H L H L H BA Column L Column 1, 2, 3
Read with Auto-Precharge H H L H L H BA Column H Column 1, 2, 3
No Operation H X L H H H X X X X 1
Device Deselect H X HXXXX X X X1
Power Down Entry H L
HXXX
XXXX1, 4
LHHH
Power Down Exit L H
HXXX
XXXX1, 4
LHHH