Datasheet

SM646UDR26485-2-I
January 31, 2006
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12
DDR2-400
M7 Mode
0Normal
1Test
Mode Register Table Definition
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst
length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM useful for vari-
ous applications. The default value of the mode register is not defined, therefore the mode register must be written after power-
up for proper operation. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#, BA0 and BA1, while control-
ling the state of address pins A0~A15. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing
into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the
mode register. The mode register contents can be changed using the same command and clock cycle requirements during nor-
mal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on
functionality. Burst length is defined by A0~A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible
with DDR SDRAM. Burst address sequence type is defined by A3, CAS latency is defined by A4~A6. The DDR2 doesn’t sup-
port half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS opera-
tion. Write recovery time tWR is defined by A9~A11.
BA2 BA1 BA0 A15~A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
M18 M17 M16 M15~M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Mode Register
0
1
MR
0
1
0 PD WR DLL TM CAS Latency BT Burst Length
M8 DLL Reset
0No
1Yes
Burst Length
M2 M1 M0 BL
0104
0118
CAS Latency
M6 M5 M4 Latency
000 Reserved
001 Reserved
0 1 0 2.0 (optional)
011 3.0
100 4.0
101 5.0
110 Reserved
111 Reserved
Write recovery for autoprecharge
M11 M10 M9
WR (cycles)
2
0 0 0 Reserved
001 2
010 3
011 4
100 5
101 6
1 1 0 Reserved
1 1 1 Reserved
M3 Burst Type
0 Sequential
1 Interleave
M12 Active power
down exit time
0 Fast exit (t
XARD
)
1 Slow exit (t
XARDS
)
M17 M16 MRS mode
00 MRS
0 1 EMRS (1)
1 0 EMRS (2): Reserved
1 1 EMRS (3): Reserved
Notes:
1. BA2 and A14~A15 are reserved for future use and must be programmed to 0 when setting the mode register.
2. WR min is determinedby t
CK
max and WR max is determined by t
CK
min. WR in clock cycles is calculated by dividing tWR (in ns) by tCK
(in ns) and rounding up to the next integer. The mode register must be programmed to this value.
DDR2-533 DDR2-667 DDR2-800