Datasheet

SM646UDR26485-2-I
January 31, 2006
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:[phone] • Fax:[phone] • E-mail: [e-mail]
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10
Serial Presence Detect Table (Contd.)
Byte No. Byte Description Value Supported Value in Hex
27 Minimum row precharge time (=tRP) 15ns 3Ch
28 Minimum row active to row active delay (=tRRD) 7.5ns 1Eh
29 Minimum RAS to CAS delay (=tRCD) 15ns 3Ch
30 Minimum activate precharge time (=tRAS) 45ns 2Dh
31 Module row density 512MB 80h
32 Command and Address signal input setup time 0.20ns 20h
33 Command and Address signal input hold time 0.27ns 27h
34 Data signal input setup time 0.10ns 10h
35 Data signal input hold time 0.17ns 17h
36 Write recovery time (=tWR) 15ns 3Ch
37 Internal write to read command delay (=tWTR) 7.5ns 1Eh
38 Internal read to precharge delay (=tRTP) 7.5ns 1Eh
39 Memory Analysis Probe Characteristics - 00h
40 Extension of tRC and tRFC None 00h
41 Device Minimum activate/auto-refresh time (=tRC) 60ns 3Ch
42 Device Minimum auto-refresh to active/auto-refresh
time (=tRFC)
105ns 69h
43 Maximum device cycle time (=tCK max) 8ns 80h
44 Device DQS-DQ skew for DQS and associated DQ
signals (=tDQSQ max)
0.24ns 18h
45 Device read data hold skew factor (=tQHS) 0.34ns 22h
46 PLL relock time - 00h
47 T
CASE.MAX
Delta / ∆T
4R4W
Delta 95°C, 1.2°C53h
48 Psi
T-A DRAM
60°C/W 78h
49 ∆T
0
DT0 5.4°C, 2x refresh,
High Temp. Self-Refresh
4Bh
50 ∆T
2N
(DT2N, UDIMM) or ∆T
2Q
(DT2Q, RDIMM) 5.7°C39h
51 ∆T
2P
(DT2P) 0.57°C26h
52 ∆T
3N
(DT3N) 5.7°C26h