Specifications

Digital I/O Ports Register Implementation on ’240x Devices

5-2

5.1 Digital I/O Ports Register Implementation on ’240x Devices

Table 5–1 lists the registers available to the digital I/O module as implemented

on the ’240x devices. These registers are memory-mapped to data space from

7090h through 709Fh. All reserved registers and bits are unimplemented:

reads return zero and writes have no effect.

Note that when multiplexed I/O pins are configured for peripheral functions or

as GPIO outputs, the pin status can be monitored by reading the I/O data

Figure 5–1. Shared Pin Configuration

Primary

Function

(Read/Write)

IOP Data Bit

In Out

0 = Input

1 = Output

MUX Control Bit

0 = I/O Function

1 = Primary Function

IOP DIR Bit

Primary Function

or I/O Pin

(MCRx.n)