Specifications

Low-Power Modes
4-5 Clocks
4.4.2.4 Peripheral interrupts
All peripheral interrupts, if enabled locally and globally, can cause the device
to exit IDLE1 mode. INTM must be enabled for LPM operation. If the IMR bits
are not enabled, the device “wakes up” from LPM mode and executes the next
instruction. Since no ISRs are executed, the peripheral flags must be cleared.
For example, when XINT1 is used to “wake up” the device from LPM0, two
things can happen based on how the XINT1 interrupt is configured. If the
XINT1 interrupt is enabled (by setting the appropriate bit in the XINT1CR regis-
ter and bit 0 in IMR is set to 1) and INTM bit is zero, a valid XINT1 signal will
first take the device out of LPM0 and will also force the device to the appropri-
ate interrupt vector. However, if the XINT1 interrupt is not enabled (by virtue
of INTM bit or bit 0 of IMR), upon a XINT1 interrupt, the DSP would “wake up”
and continue executing the instruction following the IDLE instruction.