Specifications

Low-Power Modes
4-4
Table 4–1. Low-Power Modes Summary
Low-Power
Mode
LPMx Bits
SCSR[12:13]
CPU
Clock
Domain
System
Clock
Domain
WDCLK
Status
PLL
Status
OSC
Status
Exit Condition
CPU running
normally
XX On On On On On —
IDLE1 – (LPM0) 00 Off On On On On
Peripheral inter-
rupts, XINT1/2,
Reset, PDPINTA/B
IDLE2 – (LPM1) 01 Off Off On On On
Wakeup interrupts,
Watchdog, XINT1/2,
Reset, PDPINTA/B
HALT – (LPM2)
{PLL/OSC
power down}
1X Off Off Off Off Off
Watchdog, Reset,
PDPINTA/B
4.4.2 Wake Up from Low-Power Modes
4.4.2.1 Reset
A reset (from any source) causes the device to exit any of the Idle modes. If
the device is halted, the reset initially starts the oscillator; however, initiation
of the CPU reset sequence may be delayed while the oscillator powers up be-
fore clocks are generated.
4.4.2.2 External interrupts
The external interrupts, XINTx, can cause the device to exit any of the low-
power modes, except HALT. If the device is in IDLE2 mode, the synchronous
logic connected to the external interrupt pins is bypassed with combinatorial
logic that recognizes the interrupt on the pin, starts the clocks, and then allows
the clocked logic to generate an interrupt request to the PIE controller.
4.4.2.3 Wake Up Interrupts
Some peripherals have the capability to start the device clocks and then gener-
ate an interrupt in response to certain external events, such as activity on a
communication line. As an example, the CAN wake up interrupt can assert the
CAN error interrupt request even when there are no clocks running.