Specifications

Low-Power Modes

4-3

Clocks

4.3.1 Watchdog Suspend

WDCLK is stopped when the CPU’s suspend signal goes active. This is

achieved by stopping the clock input to the clock divider which generates

WDCLK from CLKIN.

4.4 Low-Power Modes

The ’240x has an IDLE instruction. When executed, the IDLE instruction stops

the clocks to all circuits in the CPU; however, the clock output from the CPU

continues to run. With this instruction, the CPU clocks can be shut down to

save power. The CPU exits the IDLE state if reset, or if it receives an interrupt

request.

4.4.1 Clock Domains

All ’240x-based devices have two clock domains:

- The CPU clock domain consists of the clock for most of the CPU logic.

- The System clock domain consists of the peripheral clock (which is de-

rived from CLKOUT of the CPU) and the clock for the interrupt logic in the

CPU.

When the CPU goes into IDLE mode, the CPU clock domain is stopped while

the system clock domain continues to run. This mode is also known as IDLE1

mode. The ’240x CPU also contains support for a second IDLE mode, IDLE2,

implemented in external logic. By asserting the IDLE2 input to the ’240x CPU,

both the CPU clock domain and the system clock domain are stopped, allow-

ing further power savings. A third low-power mode, HALT mode, which is the

deepest mode, is possible if the oscillator and WDCLK are also shut down. In

HALT mode, the input clock to the PLL is shut off.

There are two control bits, LPM (1:0) that specify which of the three possible

low-power modes is entered when the IDLE instruction is executed. This is de-

scribed in Table 4–1. These bits are located in the “System Control and Status