Specifications

Pins
4-2
4.1 Pins
There are three device pins associated with clocks:
- XTAL1/CLKIN – This is the clock input from the external crystal to the on-
chip oscillator. If an external oscillator is used, its output must be con-
nected to this pin.
- XTAL2 – This is the clock output from the on-chip oscillator to drive the ex-
ternal crystal.
- CLKOUT/IOPE0 – This is the clock output pin. It is multiplexed with GPIO
pin IOPE0. This pin can be used to output the device (CPU) clock or the
watchdog timer clock. The clock select control bits are in the “System Con-
trol and Status Register 1 (SCSR1)”, described in section 2.2.1 on
page 2-3. This pin is configured to output CLKOUT from the CPU following
a device reset.
4.2 Phase-Locked Loop
The PLL used in the ’240x devices is different than the one used in the ’24x
devices. The ’240x PLL supports multiplication factors ranging from 0.5 to
4 times the input clock frequency. The ’240x PLL also needs external R, C
components. (See device data sheet for more details.) A bypass capacitor
(0.1 µF to 0.01 µF, ceramic) should be connected between the PLLV
CCA
and
V
SS
pins. All PCB traces pertaining to the PLL circuit must be kept as short as
possible. In addition, the loop area formed by the loop filter components, PCB
traces, and DSP chip should be as small as possible. The lead lengths of the
loop filter components must be kept as short as possible.
4.3 Watchdog Timer Clock
A low frequency clock, WDCLK, is used to clock the watchdog timer. WDCLK
has a nominal frequency of 58593.8 Hz when CPUCLK = 30 MHz. WDCLK is
derived from the CLKOUT of the CPU. This ensures that the watchdog timer
continues to count when the CPU is in IDLE1 or IDLE 2 mode (see section 4.4,
Low-Power Modes , on page 4-3).
The WDCLK is generated in the watchdog timer peripheral.
WDCLK
CLKOUT
512
=
Pins / Phase-Locked Loop / Watchdog Timer Clock