Specifications

4-1
Clocks
The ’240x devices use the phase-locked loop (PLL) circuit embedded in the
’240x CPU core to synthesize the on-chip clocks from a lower frequency exter-
nal clock. There is no means of bypassing the PLL.
Topic Page
4.1 Pins 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Phase-Locked Loop 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Watchdog Timer Clock 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Low-Power Modes 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 4