Specifications

Wait-State Generation

3-23

Memory

Table 3–3. Setting the Number of Wait States With the ’240x WSGR Bits

ISWS Bits DSWS PSWS

8 7 6

I/O WS

4 3

Data WS

1 0

Prog WS

0 0 0 0 0 0 0 0 0 0 0 0

001 1 001 1 001 1

0 1 0 2 0 1 0 2 0 1 0 2

011 3 011 3 011 3

1 0 0 4 1 0 0 4 1 0 0 4

101 5 101 5 101 5

1 1 0 6 1 1 0 6 1 1 0 6

1 1 7 1 1 1 7 1 1 1 7

In summary, while the READY signal remains high,the wait-state generator in-

serts from zero to seven wait states to a given memory space, depending on

the values of PSWS, DSWS, and ISWS. The READY signal may then be driv-

en low to generate additional wait states. If m is the number of CLKOUT cycles

required for a particular read or write operation and w is the number of wait

states added, the operation will take (m + w) cycles. At reset, all WSGR bits

are set to 1, making seven wait states the default for every memory space.