Specifications

Wait-State Generation
3-22
Figure 3–13. ’240x Wait-State Generator Control Register (WSGR) —
I/O-Space Address FFFFh (’240x)
15–11 10–9 8–6 5–3 2–0
Reserved BVIS ISWS DSWS PSWS
0 W-11 W-111 W-111 W-111
Note: 0 = Always read as zeros: W = Write access: -n = value after reset
Bits 15–11 Reserved. Bits 15–11 are reserved and always read as 0s.
Bits 10–9 Bus visibility modes. Bits 10–9 allow selection of various bus visibility modes
while running from internal program and/or data memory. These modes pro-
vide a method of tracing internal bus activity.
Bit 10 Bit 9 Visibility mode
0 0 Bus visibility OFF (reduces power and noise)
0 1 Bus visibility OFF (reduces power and noise)
1 0 Data-address bus output to external address bus
Data-data bus output to external data bus
1 1 Program-address bus o/p to external address bus
Program-data bus output to external data bus
Bits 8–6 ISWS — I/O-space wait-state bits. Bits 8-6 determine the number of wait
states (0–7) that are applied to reads from and writes to off-chip I/O space. At
reset, the three ISWS bits become 111, setting seven wait states for reads from
and writes to off-chip I/O space.
Bits 5–3 DSWS — Data-space wait-state bits. Bits 5–3 determine the number of wait
states (0–7) that are applied to reads from and writes to off-chip data space.
At reset, the three DSWS bits become 111, setting seven wait states for reads
from and writes to off-chip data space.
Bits 2–0 PSWS — Program-space wait-state bits. Bits 2-0 determine the number of
wait states (0–7) that are applied to reads from and writes to off-chip program
space. At reset, the three PSWS bits become 111, setting seven wait states
for reads from and writes to off-chip program space.
Table 3–3 shows how to set the number of wait states you want for each type
of off-chip memory.