Specifications

Wait-State Generation
3-21 Memory
3.10 Wait-State Generation
Wait states are necessary when you want to interface the ’240x with slower
external logic and memory. By adding wait states, you lengthen the time the
CPU waits for external memory or an external I/O port to respond when the
CPU reads from or writes to that memory or port. Specifically, the CPU waits
one extra cycle (one CLKOUT cycle) for every wait state. The wait states oper-
ate on CLKOUT cycle boundaries.
To avoid bus conflicts, writes from the ’240x always take at least two
CLKOUT cycles. The ’240x offers two options for generating wait states:
- The READY signal. With the READY signal, you can externally generate
any number of wait states.
- The on-chip wait-state generator. With this generator, you can generate
zero to seven wait states.
3.10.1 Generating Wait States With the READY Signal
When READY is low, the ’240x waits one CLKOUT cycle and checks READY
again. The ’240x will not continue executing until READY is driven high; there-
fore, if the READY signal is not used, it should be pulled high during external
accesses.
The READY pin can be used to generate any number of wait states. However,
when the ’240x operates at full speed, it cannot respond fast enough to provide
a READY-based wait state for the first cycle. For extended wait states using
external READY logic, the on-chip wait-state generator must be programmed
to generate at least one wait state.
Note: The READY pin has no effect on accesses to
internal memory.
3.10.2 Generating Wait States With the ’240x Wait-State Generator
The software wait-state generator can be programmed to generate zero to
seven wait states for a given off-chip memory space (program, data, or I/O),
regardless of the state of the READY signal. This wait-state generator has the
bit fields shown in Figure 3–13 and described after the figure.