Specifications

Program and Data Spaces
3-20
3.8 Program and Data Spaces
PS and STRB are inactive (high) for accesses to on-chip program memory and
data memory. The external data and address busses are active only when ac-
cesses are made to external memory locations, except when in bus visibility
(BVIS) mode (see section 3.10, Wait-State Generation ).
Two cycles are required on all external writes, including a half-cycle before WE
goes low and a half-cycle after WE goes high. This prevents data contention
on the external buses.
3.9 I/O Space
I/O space accesses are distinguished from program and data memory
accesses by IS going low. All 64K I/O words (external I/O port and on-chip I/O
registers) are accessed via the IN and OUT instructions.
While accesses are made to the on-chip I/O mapped registers, signals IS and
STRB are made inactive, that is, driven to the high state. The external address
and data bus is only active when accesses are made to external I/O memory
locations.
Two cycles are required on all external writes, including a half-cycle before WE
goes low and a half-cycle after WE goes high. This prevents data contention
on the external busses.
Program and Data Spaces / I/O Space