Specifications

Data Memory
3-14
Figure 3–9. Data Memory Pages
Data Memory
Page 0: 0000h–007Fh
Page 1: 0080h–00FFh
Page 2: 0100h–017Fh
Page 511: FF80h–FFFFh
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000 0000
OffsetDP Value
0000 0000 0
111 1111
0000 0000 0
0000 0000 1
0000 0000 1
1111 1111 1
1111 1111 1
000 0000
111 1111
000 0000
111 1111
0000 0001 0
000 0000
111 1111
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0000 0001 0
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Data Page 0 Address Map
The data memory also includes the device’s memory-mapped registers
(MMR), which reside at the top of data page 0 (addresses 0000h–007Fh).
Note the following:
- The two registers that can be accessed with zero wait states are:
J Interrupt mask register (IMR)
J Interrupt flag register (IFR)
- The test/emulation reserved area is used by the test and emulation sys-
tems for special information transfers.
Do Not Write to Test/Emulation Addresses
Writing to the test/emulation addresses can cause the device to
change its operating mode, and therefore, affect the operation of
an application.