Specifications

Overview of Memory and I/O Spaces
3-3 Memory
3.3 Overview of Memory and I/O Spaces
The ’240x design is based on an enhanced Harvard architecture. These de-
vices have multiple memory spaces accessible on three parallel buses: a pro-
gram address bus (PAB), a data-read address bus (DRAB), and a data-write
address bus (DWAB). Each of the three buses access different memory
spaces for different phases of the device’s operation. Because the bus opera-
tions are independent, it is possible to access both the program and data
spaces simultaneously. Within a given machine cycle, the CALU can execute
as many as three concurrent memory operations.
The ’240x address map is organized into three individually selectable spaces:
- Program memory (64K words) contains the instructions to be executed,
as well as immediate data used during program execution.
- Data memory (64K words) holds data used by the instructions.
- Input/output (I/O) space (64K words) interfaces to external peripherals
and may contain on-chip registers.
These spaces provide a total address space of 192K words. The ’240x devices
include on-chip memory to aid in system performance and integration.
The advantages of operating from on-chip memory are:
- Higher performance than external memory (because the wait states re-
quired for slower external memories are avoided)
- Lower cost than external memory
- Lower power consumption than external memory
The advantage of operating from external memory is the ability to access a
larger address space. Only the ’2407 has an external memory interface. Other
devices have only on-chip memory. Figure 3–1 through Figure 3–6 depict the
memory map of ’240x devices.
Access to an illegal address will generate an NMI.