Specifications

External Interrupt Control Registers
2-37 System Configuration and Interrupts
2.13.2 External Interrupt 2 Control Register (XINT2CR)
Figure 2–18. External Interrupt 2 Control Register (XINT2CR) — Address 7071h
15 14–3 2 1 0
XINT2 flag
Reserved XINT2 polarity XINT2 priority XINT2 enable
RC-0 R-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, C = Clear by writing a 1, -0 = value after reset
Bit 15 XINT2 Flag
This bit indicates whether the selected transition has been detected on the
XINT2 pin, and is set whether or not the interrupt is enabled. This bit is cleared
by the appropriate interrupt acknowledge, by software writing a 1 (writing a 0
has no effect), or by a device reset.
0 No transition detected
1 Transition detected
Bits 14–3 Reserved. Reads return zero; writes have no effect.
Bit 2 XINT2 Polarity
This read/write bit determines whether interrupts are generated on the rising
edge or the falling edge of a signal on the pin.
0 Interrupt generated on a falling edge (high-to-low transition).
1 Interrupt generated on a rising edge (low-to-high transition).
Bit 1 XINT2 Priority
This read/write bit determines which interrupt priority is requested. The CPU
interrupt priority levels corresponding to low and high priority are coded into
the peripheral interrupt expansion controller. These priority levels are shown
in Table 2–2,
’240x Interrupt Source Priority and Vectors, in Chapter 2, on
page 2-8.
0 High priority
1 Low priority
Bit 0 XINT2 Enable
This read/write bit enables or disables the external interrupt XINT2.
0 Disable Interrupt
1 Enable interrupt