Specifications

Reset
2-35 System Configuration and Interrupts
2.11 Reset
The ’240x devices have two sources of reset:
- An external reset pin
- A watchdog timer timeout
The reset pin is an I/O pin. If there is an internal reset event (watchdog timer),
the reset pin is put into output mode and driven low to indicate to external cir-
cuits that the ’240x device is resetting itself.
The external reset pin and watchdog timer reset are ORed together to drive
the reset input to the CPU.
2.12 Illegal Address Detect
The decode logic has the capability to detect accesses to illegal addresses (all
unimplemented addresses including reserved registers in each peripheral’s
memory map). The occurrence of an illegal access sets the illegal address flag
(ILLADR) in the “System Control and Status Register 1” (SCSR1). See sec-
tion 2.2.1,
System Control and Status Registers 1 and 2 (SCSR1, SCSR2) , on
page 2-3. The detection of an illegal address generates a nonmaskable inter-
rupt (NMI). The illegal address condition is asserted whenever illegal address-
es are accessed. The illegal address flag (ILLADR) remains set following an
illegal address condition until it is cleared by software. A check for illegal ad-
dress access is made for data memory space only.
Reset / Illegal Address Detect