Specifications

Peripheral Interrupt Registers
2-33 System Configuration and Interrupts
Bit 15 Reserved. Reads return zero; writes have no effect.
Bits 14–0 IACK1.14–IACK1.0. Bit behavior is the same as that of PIACKR0.
Table 2–7. Peripheral Interrupt Acknowledge Descriptions (PIACKR1)
Bit position Interrupt Interrupt Description Interrupt Level
IAK 1.0 T2PINT Timer 2 period interrupt INT3
IAK 1.1 T2CINT Timer 2 compare interrupt INT3
IAK 1.2 T2UFINT Timer 2 underflow interrupt INT3
IAK 1.3 T2OFINT Timer 2 overflow interrupt INT3
IAK 1.4 CAPINT1 Capture 1 interrupt INT4
IAK 1.5 CAPINT2 Capture 2 interrupt INT4
IAK 1.6 CAPINT3 Capture 3 interrupt INT4
IAK 1.7 SPIINT SPI interrupt. Low priority INT5
IAK 1.8 RXINT SCI receiver interrupt. Low priority INT5
IAK 1.9 TXINT SCI transmitter interrupt. Low priority INT5
IAK 1.10 CANMBINT CAN mailbox interrupt. Low priority INT5
IAK 1.11 CANERINT CAN error interrupt. Low priority INT5
IAK 1.12 ADCINT ADC Interrupt. Low priority INT6
IAK 1.13 XINT1 External Interrupt pin 1. Low priority INT6
IAK 1.14
XINT2 External Interrupt pin 2. Low priority INT6
Figure 2–16. Peripheral Interrupt Acknowledge Register 2 (PIACKR2) — Address 7016h
15 14 13 12 11 10 9 8
IAK2.15 IAK2.14 IAK2.13 IAK2.12 IAK2.11 IAK2.10 IAK2.9 IAK2.8
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
76543210
IAK2.7
IAK2.6 IAK2.5 IAK2.4 IAK2.3 IAK2.2 IAK2.1 IAK2.0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Note: R = read access; W = write access; value following dash (–) is value after reset
Bits 15–0 IACK2.15–IACK2.0. Bit behavior is the same as that of PIACKR0.