Specifications

Peripheral Interrupt Registers
2-32
Bits 15–0 IACK0.15–IACK0.0. Peripheral interrupt acknowledge bits. Writing a 1
causes the corresponding peripheral interrupt acknowledge to be asserted,
which clears the corresponding peripheral interrupt request. Note that assert-
ing the interrupt acknowledge by writing to this register does not update the
PIVR. Reading the register always returns zeros.
Table 2–6. Peripheral Interrupt Acknowledge Descriptions (PIACKR0)
Bit position Interrupt Interrupt Description Interrupt Level
IAK 0.0 PDPINT Power Device Protection interrupt pin INT1
IAK 0.1 ADCINT ADC Interrupt. High priority INT1
IAK 0.2 XINT1 External Interrupt pin 1. High priority INT1
IAK 0.3 XINT2 External Interrupt pin 2. High priority INT1
IAK 0.4 SPIINT SPI interrupt. High priority INT1
IAK 0.5 RXINT SCI receiver interrupt. High priority INT1
IAK 0.6 TXINT SCI transmitter interrupt. High priority INT1
IAK 0.7 CANMBINT CAN mailbox interrupt. High priority INT1
IAK 0.8 CANERINT CAN error interrupt. High priority INT1
IAK 0.9 CMP1INT Compare 1 interrupt INT2
IAK 0.10 CMP2INT Compare 2 interrupt INT2
IAK 0.11 CMP3INT Compare 3 interrupt INT2
IAK 0.12 T1PINT Timer 1 period interrupt INT2
IAK 0.13 T1CINT Timer 1 compare interrupt INT2
IAK 0.14 T1UFINT Timer 1 underflow interrupt INT2
IAK 0.15
T1OFINT Timer 1 overflow interrupt INT2
Figure 2–15. Peripheral Interrupt Acknowledge Register 1 (PIACKR1) — Address 7015h
15 14 13 12 11 10 9 8
Reserved IAK1.14 IAK1.13 IAK1.12 IAK1.11 IAK1.10 IAK1.9 IAK1.8
R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
IAK1.7
IAK1.6 IAK1.5 IAK1.4 IAK1.3 IAK1.2 IAK1.1 IAK1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset