Specifications

Peripheral Interrupt Registers
2-31 System Configuration and Interrupts
Table 2–5. Peripheral Interrupt Request Descriptions (PIRQR2)
Bit position Interrupt Interrupt Description Interrupt Level
IRQ 2.0 PDPINTB Power drive protection interrupt pin INT1
IRQ 2.1 CMP4INT Compare 4 interrupt INT2
IRQ 2.2 CMP5INT Compare 5 interrupt INT2
IRQ 2.3 CMP6INT Compare 6 interrupt INT2
IRQ 2.4 T3PINT Timer 3 period interrupt INT2
IRQ 2.5 T3CINT Timer 3 compare interrupt INT2
IRQ 2.6 T3UFINT Timer 3 underflow interrupt INT2
IRQ 2.7 T3OFINT Timer 3 overflow interrupt INT2
IRQ 2.8 T4PINT Timer 4 period interrupt INT3
IRQ 2.9 T4CINT Timer 4 compare interrupt INT3
IRQ 2.10 T4UFINT Timer 4 underflow interrupt INT3
IRQ 2.11 T4OFINT Timer 4 overflow interrupt INT3
IRQ 2.12 CAP4INT Capture 4 interrupt INT4
IRQ 2.13 CAP5INT Capture 5 interrupt INT4
IRQ 2.14
CAP6INT Capture 6 interrupt INT4
2.10.3 Peripheral Interrupt Acknowledge Registers (PIACKR0 ,1, 2)
The peripheral interrupt acknowledge registers (PIACKRx) are memory
mapped to enable an easy test of the peripheral interrupt acknowledges.
There are three of these 16-bit registers; and therefore, the PIE controller can
support up to 48 peripheral interrupts. These registers are generally used for
test purposes only and are not for user applications. PIACKR0 is shown in
Figure 2–14, PIACKR1 is shown in Figure 2–15, and PIACKR2 is shown in
Figure 2–16.
Figure 2–14. Peripheral Interrupt Acknowledge Register 0 (PIACKR0) — Address 7014h
15 14 13 12 11 10 9 8
IAK0.15
IAK0.14 IAK0.13 IAK0.12 IAK0.11 IAK0.10 IAK0.9 IAK0.8
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
IAK0.7
IAK0.6 IAK0.5 IAK0.4 IAK0.3 IAK0.2 IAK0.1 IAK0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset