Specifications

Peripheral Interrupt Registers
2-30
Table 2–4. Peripheral Interrupt Request Descriptions (PIRQR1)
Bit position Interrupt Interrupt Description Interrupt Level
IRQ 1.0 T2PINT Timer 2 period interrupt INT3
IRQ 1.1 T2CINT Timer 2 compare interrupt INT3
IRQ 1.2 T2UFINT Timer 2 underflow interrupt INT3
IRQ 1.3 T2OFINT Timer 2 overflow interrupt INT3
IRQ 1.4 CAP1INT Capture 1 interrupt INT4
IRQ 1.5 CAP2INT Capture 2 interrupt INT4
IRQ 1.6 CAP3INT Capture 3 interrupt INT4
IRQ 1.7 SPIINT SPI interrupt. Low priority INT5
IRQ 1.8 RXINT SCI receiver interrupt. Low priority INT5
IRQ 1.9 TXINT SCI transmitter interrupt. Low priority INT5
IRQ 1.10 CANMBINT CAN mailbox interrupt. Low priority INT5
IRQ 1.11 CANERINT CAN error interrupt. Low priority INT5
IRQ 1.12 ADCINT ADC Interrupt. Low priority INT6
IRQ 1.13 XINT1 External Interrupt pin 1. Low priority INT6
IRQ 1.14
XINT2 External Interrupt pin 2. Low priority INT6
Figure 2–13. Peripheral Interrupt Request Register 2 (PIRQR2) — Address 7012h
15 14 13 12 11 10 9 8
IRQ2.15 IRQ2.14 IRQ2.13 IRQ2.12 IRQ2.11 IRQ2.10 IRQ2.9 IRQ2.8
R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
IRQ2.7
IRQ2.6 IRQ2.5 IRQ2.4 IRQ2.3 IRQ2.2 IRQ2.1 IRQ2.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, -0 = value after reset
Bits 15–0 IRQ2.15–IRQ2.0
0 Corresponding peripheral interrupt is not pending.
1 Peripheral Interrupt is pending.
Note: Writing a 1 sends IRQ to core; writing a 0 has no effect.