Specifications

Peripheral Interrupt Registers
2-29 System Configuration and Interrupts
Table 2–3. Peripheral Interrupt Request Descriptions (PIRQR0) (Continued)
Bit position Interrupt LevelInterrupt DescriptionInterrupt
IRQ 0.10 CMP2INT Compare 2 interrupt INT2
IRQ 0.11 CMP3INT Compare 3 interrupt INT2
IRQ 0.12 T1PINT Timer 1 period interrupt INT2
IRQ 0.13 T1CINT Timer 1 compare interrupt INT2
IRQ 0.14 T1UFINT Timer 1 underflow interrupt INT2
IRQ 0.15
T1OFINT Timer 1 overflow interrupt INT2
Figure 2–12. Peripheral Interrupt Request Register 1 (PIRQR1) — Address 7011h
15 14 13 12 11 10 9 8
Reserved IRQ1.14 IRQ1.13 IRQ1.12 IRQ1.11 IRQ1.10 IRQ1.9 IRQ1.8
R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
IRQ1.7
IRQ1.6 IRQ1.5 IRQ1.4 IRQ1.3 IRQ1.2 IRQ1.1 IRQ1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 15 Reserved. Reads return zero, writes have no effect.
Bits 14–0 IRQ1.14–IRQ1.0
0 Corresponding peripheral interrupt is not pending.
1 Peripheral Interrupt is pending.
Note: Writing a 1 sends IRQ to core; writing a 0 has no effect.