Specifications

Peripheral Interrupt Registers
2-28
2.10.2 Peripheral Interrupt Request Registers (PIRQR0, 1, 2)
The peripheral interrupt request registers (PIRQRx) enable:
- The state of the peripheral interrupt requests to be read
- A simulated assertion of a particular peripheral interrupt request
PIRQR0 is shown in Figure 2–11, PIRQR1 is shown in Figure 2–12, and
PIRQR2 is shown in Figure 2–13.
Figure 2–11.Peripheral Interrupt Request Register 0 (PIRQR0) — Address 7010h
15 14 13 12 11 10 9 8
IRQ0.15
IRQ0.14 IRQ0.13 IRQ0.12 IRQ0.11 IRQ0.10 IRQ0.9 IRQ0.8
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
IRQ0.7
IRQ0.6 IRQ0.5 IRQ0.4 IRQ0.3 IRQ0.2 IRQ0.1 IRQ0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–0 IRQ0.15–IRQ0.0
0 Corresponding peripheral interrupt is not pending.
1 Peripheral Interrupt is pending.
Note: Writing a 1 sends IRQ to core; writing a 0 has no effect.
Table 2–3. Peripheral Interrupt Request Descriptions (PIRQR0)
Bit position Interrupt Interrupt Description Interrupt Level
IRQ 0.0 PDPINTA Power device protection interrupt pin INT1
IRQ 0.1 ADCINT ADC Interrupt. High priority INT1
IRQ 0.2 XINT1 External Interrupt pin 1. High priority INT1
IRQ 0.3 XINT2 External Interrupt pin 2. High priority INT1
IRQ 0.4 SPIINT SPI interrupt. High priority INT1
IRQ 0.5 RXINT SCI receiver interrupt. High priority INT1
IRQ 0.6 TXINT SCI transmitter interrupt. High priority INT1
IRQ 0.7 CANMBINT CAN mailbox interrupt. High priority INT1
IRQ 0.8 CANERINT CAN error interrupt. High priority INT1
IRQ 0.9
CMP1INT Compare 1 interrupt INT2