Specifications

Peripheral Interrupt Registers
2-27 System Configuration and Interrupts
2.10 Peripheral Interrupt Registers
The peripheral interrupt registers include the following:
- The peripheral interrupt vector register (PIVR)
- The peripheral interrupt request register 0 (PIRQR0)
- The peripheral interrupt request register 1 (PIRQR1)
- The peripheral interrupt request register 2 (PIRQR2)
- The peripheral interrupt acknowledge register 0 (PIACKR0)
- The peripheral interrupt acknowledge register 1 (PIACKR1)
- The peripheral interrupt acknowledge register 2 (PIACKR2)
PIRQR0/1/2 and PIACKR0/1/2 are control registers internal to PIE
module for generating interrupts (INT1 – INT6) to the CPU. While
programming, these registers can be ignored as they monitor the
internal operation of the PIE. These registers are generally used for
test purposes.
2.10.1 Peripheral Interrupt Vector Register (PIVR)
The peripheral interrupt vector register (PIVR) is a 16-bit read-only register. It
is located at address 701Eh (in data space).
During the peripheral interrupt acknowledge cycle, the PIVR is loaded with the
interrupt vector of the highest-priority pending interrupt associated with the
CPU interrupt (INTn) being acknowledged (or the phantom interrupt vector).
The PIVR is shown in Figure 2–10.
Figure 2–10. Peripheral Interrupt Vector Register (PIVR)— Address 701Eh
15 14 13 12 11 10 9 8
V15
V14 V13 V12 V11 V10 V9 V8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
76543210
V7
V6 V5 V4 V3 V2 V1 V0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Note: R = Read access; -0 = value after reset
Bits 15–0 V15–V0. Interrupt vector. This register contains the peripheral interrupt vector
of the most recently acknowledged peripheral interrupt.