Specifications

CPU Interrupt Registers
2-26
Bit 1 INT2. Interrupt 2 mask. This bit masks or unmasks interrupt level INT2.
0 Level INT2 is masked.
1 Level INT2 is unmasked.
Bit 0 INT1. Interrupt 1 mask. This bit masks or unmasks interrupt level INT1.
0 Level INT1 is masked.
1 Level INT1 is unmasked.
Note: The IMR bits are not affected by a device reset.