Specifications

CPU Interrupt Registers
2-25 System Configuration and Interrupts
2.9.2 Interrupt Mask Register (IMR)
The IMR is a 16-bit, memory-mapped register located at address 0004h in
data memory space. The IMR contains mask bits for all the maskable interrupt
levels (INT1–INT6). Neither NMI nor RS is included in the IMR; thus, IMR has
no effect on these interrupts.
You can read the IMR to identify masked or unmasked interrupt levels, and you
can write to the IMR to mask or unmask interrupt levels. To unmask an interrupt
level, set its corresponding IMR bit to 1. To mask an interrupt level, set its corre-
sponding IMR bit to 0. When an interrupt is masked, it is not acknowledged,
regardless of the value of the INTM bit. When an interrupt is unmasked, it is
acknowledged if the corresponding IFR bit is 1 and the INTM bit is 0.
The IMR is shown in Figure 2–9, and descriptions of the bits follow the figure.
Figure 2–9. Interrupt Mask Register (IMR) — Address 0004h
15–6 5 4 3 2 1 0
Reserved INT6 mask INT5 mask INT4 mask INT3 mask INT2 mask INT1 mask
0 RWRWRWRWRWRW
Note: 0 = Always read as zeros, R = Read access, W = Write access, bit values are not affected by a device reset
Bits 15–6 Reserved. These bits are always read as 0s.
Bit 5 INT6. Interrupt 6 mask. This bit masks or unmasks interrupt level INT6.
0 Level INT6 is masked.
1 Level INT6 is unmasked.
Bit 4 INT5. Interrupt 5 mask. This bit masks or unmasks interrupt level INT5.
0 Level INT5 is masked.
1 Level INT5 is unmasked.
Bit 3 INT4. Interrupt 4 mask. This bit masks or unmasks interrupt level INT4.
0 Level INT4 is masked.
1 Level INT4 is unmasked.
Bit 2 INT3. Interrupt 3 mask. This bit masks or unmasks interrupt level INT3.
0 Level INT3 is masked.
1 Level INT3 is unmasked.