Specifications

CPU Interrupt Registers
2-23 System Configuration and Interrupts
2.9 CPU Interrupt Registers
The CPU interrupt registers in the upper level of heirarchy include the follow-
ing:
- The interrupt flag register (IFR)
- The interrupt mask register (IMR)
2.9.1 Interrupt Flag Register (IFR)
The interrupt flag register (IFR), a 16-bit, memory-mapped register at address
0006h in data-memory space, is used to identify and clear pending interrupts.
The IFR contains flag bits for all the maskable interrupts (INT1–INT6).
When a maskable interrupt is requested, the flag bit in the corresponding pe-
ripheral control register is set to 1. If the corresponding mask bit is also 1, the
interrupt request is sent to the CPU, setting the corresponding flag in the IFR.
This indicates that the interrupt is pending or waiting for acknowledgement.
You can read the IFR to identify pending interrupts and write to the IFR to clear
pending interrupts. To clear a single interrupt, write a 1 to the corresponding
IFR bit. All pending interrupts can be cleared by writing the current contents
of the IFR back into the IFR.
The following events also clear an IFR flag:
- The CPU acknowledges the interrupt.
- The ’240x is reset.
Notes:
1) To clear an IFR bit, you must write a 1 to it, not a 0.
2) When a maskable interrupt is acknowledged, only the IFR bit is cleared
automatically. The flag bit in the corresponding peripheral control regis-
ter is not cleared. If an application requires that the control register flag
be cleared, the bit must be cleared by software.
3) When an interrupt is requested by an INTR instruction and the corre-
sponding IFR bit is set, the CPU does not clear the bit automatically. If
an application requires that the IFR bit be cleared, the bit must be cleared
by software.
4) IMR and IFR registers pertain to core-level interrupts. All peripherals
have their own interrupt mask and flag bits in their respective control/
configuration registers. Note that several peripheral interrupts are
grouped under one core-level interrupt.