Specifications

Interrupt Latency
2-21 System Configuration and Interrupts
2.7 Interrupt Latency
There are three components to interrupt latency:
1) Synchronization is the time it takes for the request generated in response
to the occurrence of an interrupt generating event to be recognized by the
PIE controller and converted into a request to the CPU.
2) Core Latency is the time it takes for the CPU to recognize the enabled in-
terrupt request, clear it’s pipeline, and begin fetching the first instruction
from the CPU’s interrupt vector table. There is a minimum core latency of
four CPU cycles. If a higher priority maskable interrupt is requested during
this minimum latency period, it is masked until the ISR for the interrupt be-
ing serviced reenables interrupt. The latency can be longer than the mini-
mum if the interrupt request occurs during an uninterruptible operation,
e.g., a repeat loop, a multi-cycle instruction, or during a wait-stated ac-
cess. If a higher priority interrupt occurs during this additional latency peri-
od, it
gets serviced before the original lower priority interrupt, assuming
both are enabled.
3)
ISR Latency is the time it takes to get to the specific interrupt service
routine (ISR) code for the event that caused the acknowledged interrupt.
ISR latency can vary depending on how much context saving is required.