Specifications

Interrupt Operation Sequence
2-20
Figure 2–7. ’240x Interrupt Response and Flow
Interrupt generation
awaits IE to be set
or software clear of
the IF bit set in
peripheral register
Peripheral interrupt
occurs
Interrupt flag (IF)
set in peripheral
register (PR)
Interrupt enable
(IE) = 1 in PR?
IE set by S/W
PIRQ generated
to PIE
Peripheral interrupt
occurs
PIRQ triggers PIE
flags to be set and
the respective INTx
is generated
CPU receives INTx
Start
Respective
IFR bit is set
IMR bit = 1?
Interrupt generation
logic awaits IMR bit
to be set or software
clear of the IFR bit
Yes
No
INTM = 0?
Interrupt logic awaits
INTM to be cleared
CPU recognizes the
INTx and issues
interrupt acknowledge
IFR bit is cleared,
INTM is set,
PC jumps to INTx
vector address
0000–000Ch
CPU interrupt
acknowledge clears
interrupt request in
PIE (PIRQn)
PIE logic loads PIV
value into PIVR
PIE logic also
enables pending INTx
Next pending INTx
issued to CPU
Peripheral interrupt
occurs
Interrupt enable
(IE) = 1 in PR?
PIRQ generated
to PIE
Peripheral interrupt
occurs
User code saves
context, reads
PIVR for PIV value
PIV = phantom
vector?
Peripheral interrupt
occurs
No
CPU branches
to GISR
Based on PIV
branch to SISR
Interrupt service for
phantom vector
Return
SISR user code to
service the peripheral
interrupt
Based on PIV
branch to SISR
Clear IF bit in
peripheral register,
clear INTM bit
Return
Note:
IF
IE
GISR
SISR
–
–
–
–
Interrupt flag. This bit has to be cleared by s/
w
Interrupt enable
General ISR
Specific ISR
or future interrupts will be ignored.
Yes Yes
Yes
NoNo
Peripheral Flow
PIE Flow
CPU Flow
GISR Flow
SISR Flow
PR – Peripheral register, EVIFRA, etc.