Specifications

Interrupt Operation Sequence
2-19 System Configuration and Interrupts
2.6 Interrupt Operation Sequence
An interrupt generating event occurs in a peripheral. Refer to Figure 2–7 for
’240x interrupt response and flow in each module of the ’240x.The interrupt
flag (IF) bit corresponding to that event is set in a register in the peripheral. If
the corresponding interrupt enable (IE) bit is set, the peripheral generates an
interrupt request to the PIE controller by asserting its PIRQ. If the interrupt is
not enabled, the IF remains set until cleared by software. If the interrupt is en-
abled at a later time, and the interrupt flag is still set, the PIRQ will immediately
be asserted.
If no unacknowledged CPU interrupt request of the same priority level (INTn)
has previously been sent, the PIRQ causes the PIE controller to generate a
CPU interrupt request (INTn). This pulse is active low for two CPU clock
cycles.
The interrupt request to the CPU sets the corresponding flag in the CPU’s in-
terrupt flag register (IFR). If the CPU interrupt has been enabled by setting the
corresponding bit in the CPU’s interrupt mask register (IMR), the CPU stops
what it is doing, masks all other maskable interrupts by setting the INTM bit,
saves some context, and starts executing the general interrupt service routine
(GISR) for that interrupt priority level (INTn). The CPU generates an interrupt
acknowledge automatically which is accompanied by a value on the program
address bus (PAB) corresponding to the interrupt priority level being re-
sponded to. For example, if INT3 is asserted, its vector 0006h is loaded in the
PAB. This is the interrupt vector corresponding to INTn (refer to Table 2–2
’240x Interrupt Source Priority and Vectors, on page 2-8).
The PIE controller decodes the PAB value and generates a peripheral interrupt
acknowledge to clear the PIRQ bit associated with the CPU interrupt being ac-
knowledged. The PIE controller then loads the peripheral interrupt vector reg-
ister (PIVR) with the appropriate peripheral interrupt vector (or the phantom
interrupt vector), from the table stored in the PIE controller.
When the GISR has completed any necessary context saves, it reads the
PIVR and uses that interrupt vector to branch to the specific interrupt service
routine (SISR) for the interrupt event which occurred in the peripheral.
Re-enabling interrupts
Interrupts must not be reenabled until the PIVR has been read;
otherwise, it’s contents can get overwritten by a subsequent interrupt.