Specifications

Interrupt Vectors

2-17

System Configuration and Interrupts

Figure 2–6. Interrupt Requests

IMR

INTM

IFR

INT1INT6 INT5 INT4 INT3 INT2

Interrupt

acknowledge

CPU Interrupt Registers and Logic

Peripheral Interrupt Extension

PIRQ0 register

Peripheral: External Interrupt

XINT1CR register

Flag

Priority

Mask

Priority

Interrupt controller

INT1INT6 INT5 INT4 INT3 INT2

1514131211109876543210

1514131211109876543 210

1514131211109876543210

2.5.1 Phantom Interrupt Vector

The phantom interrupt vector is an interrupt system integrity feature. If the

CPU’s interrupt acknowledge is asserted, but there is no associated peripheral

interrupt request asserted, the phantom vector is used so that this fault is han-

dled in a controlled manner. The phantom interrupt vector is required when,

for example, the CPU executes a software interrupt instruction with an argu-

ment corresponding to a peripheral interrupt (usually INT1–INT6). Another ex-

ample is when a peripheral makes an interrupt request but its INTn flag was

cleared by software before the CPU acknowledged the request. In this case,

there may be no peripheral interrupt request asserted to the interrupt control-

ler; and therefore, the controller does not know which peripheral interrupt vec-

tor to load into the PIVR. In these two situations, the phantom interrupt vector

is loaded into the PIVR in lieu of a peripheral interrupt vector.