Specifications

Index
Index-9
SPI operation 9-6
introduction to operation 9-6
master mode 9-7
slave mode 9-8
SPI master/slave connection 9-7
SPI physical description 9-2
software hierarchy 2-18
SOS_synch, start of sequence sync-up) 7-34
SPI, serial peripheral interface 9-1
stop bits (1 or 2) 2-24, 2-25
T
TAn (transmission acknowledge) 10-19
TCR (transmission control register), figure 10-19
TMS320 family 1-2 to 1-6
advantages 1-2
development 1-2
history 1-2
overview 1-2
transmit mailboxes 10-13
TRRn (transmission request reset) 10-20
TRSn (transmission request set) 10-20
W
wait states, definition D-14
wake up from low power modes 4-4
external interrupts 4-4
peripheral interrupts 4-5
reset 4-4
wake up interrupts 4-4
wake up interrupts 4-4
watchdog suspend 4-3
watchdog timer (WD) 11-1
control registers 11-4
watchdog control registers 11-8
WD counter register (WDCNTR) 11-8
WD module control registers 11-8
WD overflow (timeout) selections 11-10
WD reset key register (WDKEY) 11-9
WD timer control register (WDCR) 11-9
WD timer clock 11-4
operation of WD timers 11-5
servicing the WD timer 11-5
typical WDKEY register power up
sequence 11-6
watchdog suspend 11-4
WD check bit logic 11-7
WD prescale select 11-5
WD reset 11-6
WD setup 11-7
WD timer features 11-2
block diagram of the WD module 11-3
watchdog timer clock 4-2
WDCNTR, watchdog counter register 11-8
WDCR, watchdog timer control register 11-9
WDKEY, watchdog reset key register 11-9
WSGR, ’C24x wait–state generator control regis-
ter 3-22
X
XINT1CR, XINT1 control register 2-36
XINT2CR, XINT2 control register 2-37