Specifications

Index
Index-8
port C data and direction control register
(PCDATDIR) 5-12
port C data and direction control register
(PDDATDIR), for ’C242 only 5-13
port D data and direction control register
(PDDATDIR), for ’X241 and ’X243 5-14
XINT1 control register (XINT1CR) 2-36
XINT2 control register (XINT2CR) 2-37
remote frames 10-14
remote requests
receiving 10-14
sending 10-15
reset 2-35, 4-4
RFPn (remote frame pending register) 10-21
RMLn (receive message lost) 10-21
RMPn (receive message pending) 10-22
ROM, factory masked on–chip ROM 3-2
S
sample ISR code 2-22
SCI, serial communications interface 8-1
serial communications interface (SCI) 8-1
Architecture 8-5
differences vs. ’C240 SCI 8-2
multiprocessor and asynchronous communica-
tion modes 8-7
SCI block diagram 8-4
SCI communication format 8-14
receiver signals in communication
mode 8-14
transmitter signals in communication
modes 8-15
SCI control registers 8-6, 8-19
baud–select LSbyte register
(SCILBAUD) 8-25
baud–select MSbyte register
(SCIHBAUD)s 8-25
communication control register
(SCICCR) 8-20
emulation data buffer register 8-30
priority control register (SCIPRI) 8-31
receiver data buffer (SCIRXBUF) 8-30
receiver data buffer registers 8-29
receiver status register (SCIRXST) 8-27
receiver status register (SCIRXST) bit associ-
ations 8-29
SCI CHAR2–0 bit values and character
lengths 8-21
SCI control register 1 (SCICTL1) 8-22
SCI control register 2 (SCICTL2) 8-26
SW RESET affected flags 8-23
transmit data buffer register (SCITX-
BUF) 8-30
SCI multiprocessor communication 8-9
address–bit multiprocessor mode 8-12
idle–line multiprocessor mode 8-10
SCI physical description 8-2
SCI port interrupts 8-17
SCI baud rate calculations 8-18
SCI programmable data format 8-8
SCI register address offsets 8-6
serial peripheral interface (SPI) 9-1
differences vs. ’C240 SPI 9-2
SPI block diagram 9-3
SPI control registers 9-4, 9-17
addresses of SPI control registers 9-5
character length control bit values 9-19
SPI baud rate calculations 9-23
SPI baud rate register (SPIBRR) 9-23
SPI configuration control register
(SPICCR) 9-18
SPI emulation buffer register
(SPIRXEMU) 9-24
SPI operation control register (SPICTL) 9-20
SPI priority control register (SPIPRI) 9-28
SPI serial data register (SPIDAT) 9-27
SPI serial receive buffer register
(SPIRXBUF) 9-25
SPI serial transmit buffer register
(SPITXBUF) 9-26
SPI status register (SPISTS) 9-21
SPI interrupts 9-9
data format 9-10
data transfer example 9-15
initialization upon reset 9-14
OVERRUN INT ENA bit (SPICTL.4) 9-10
RECEIVER OVERRUN flag bit
(SPISTS.7) 9-10
SPI baud rate determination 9-11
SPI clocking schemes 9-12
SPI initialization using the SPI SW RESET
bit 9-15
SPI INT ENA bit (SPICTL.0) 9-9
SPI INT Flag bit (SPISTS.6) 9-9
SPI PRIORITY bit (SPIPRI.6) 9-10
transmission of bit from SPIBUF 9-11