Specifications

Index
Index-7
off-chip memory, configuration, local data 3-15
on-chip memory
advantages 3-3
configuration 3-15
OPCn (overwrite protection control) 10-22
overview, TMS320 family 1-2
P
PADATDIR, port A data and direction control regis-
ter 5-9
PAR (program address register), definition D-10
PARITY ENABLE bit 2-24, 2-25, 2-26
PBDATDIR, port B data and direction control regis-
ter 5-11
PCDATDIR, port C data and direction control regis-
ter 5-12
PDDATDIR
port D data and direction control register 5-13
port D data and direction control register 5-14
peripheral interrupt acknowledge descriptions 2-32
peripheral interrupt acknowledge descriptions
(PIACKR1) 2-33
peripheral interrupt acknowledge register 0
(PIACKR0) 2-31
peripheral interrupt expansion (PIE) 2-12
peripheral interrupt registers 2-27
peripheral interrupt request descriptions
(PIRQR0) 2-28
peripheral interrupt request descriptions
(PIRQR1) 2-30, 2-31, 2-34
peripheral interrupt request register
(PIRQR0) 2-28
peripheral interrupt vector register (PIVR) 2-27
peripheral interrupts 4-5
peripheral set 1-5
phantom interrupt vector 2-17
phase locked loop 4-2
PIACKR0, peripheral interrupt acknowledge register
0 2-31
PIE, peripheral interrupt expansion 2-12
PIRQR0, peripheral interrupt request register
0 2-28
PIVR, peripheral interrupt vector register 2-27
port A data and direction control register
(PADATDIR) 5-9
port B data and direction control register
(PBDATDIR) 5-11
port C data and direction control register
(PCDATDIR) 5-12
port D data and direction control register 5-13
port D data and direction control register
(PDDATDIR) 5-14
program address register (PAR), definition D-10
program examples B-1
program memory 3-10
R
RCR (receive control register) 10-21
receive mailboxes 10-13
register definitions B-1
registers
capture control register (CAPCON) 6-70
capture FIFO status register 6-73
compare action control register (ACTR) 6-42
compare control register (COMCON) 6-39
dead–band timer control register
(DBTCON) 6-48
EV2 interrupt flag register A (EVIFRA) 6-85
EV2 interrupt flag register B (EVIFRB) 6-87
EV2 interrupt flag register C (EVIFRC) 6-88
EV2 interrupt mask register A (EVIMRA) 6-89
EV2 interrupt mask register B (EVIMRB) 6-90
EV2 interrupt mask register C (EVIMRC) 6-90
I/O mux control 5-5
I/O mux control register A OCRA) 5-5
I/O mux control register B (OCRB) 5-6
individual GP timer control register
(TxCON) 6-31
interrupt flag register (IFR) 2-23 to 2-38
interrupt mask register (IMR) 2-25 to 2-38
mapped to data page 0 3-15
output control register B, for F241 only 5-6, 5-8
overall GP timer control register
(GPTCON) 6-33
peripheral interrupt 2-27
peripheral interrupt acknowledge register 0
(PIACKR0) 2-31
peripheral interrupt request register 0
(PIRQR0) 2-28
peripheral interrupt vector (PIVR) 2-27
port A data and direction control register
(PADATDIR) 5-9
port B data and direction control register
(PBDATDIR) 5-11