Specifications

Index
Index-6
peripheral interrupt request descriptions
(PIRQR1) 2-30, 2-31, 2-34
peripheral interrupt request descriptions
(PIRQR0) 2-28
interrupt acknowledge 2-15
interrupt flag register (IFR) 2-23 to 2-38
interrupt latency, definition D-7
interrupt mask register (IMR) 2-25 to 2-38
interrupt priority and vectors 2-8
interrupt request structure 2-14
interrupt service routines (ISRs), definition D-7
interrupt vectors 2-16
phantom interrupt vector 2-17
interrupts
IMR register 2-25
interrupt mask register 2-25
masking, interrupt mask register (IMR) 2-25 to
2-38
pending, interrupt flag register (IFR) 2-23 to
2-38
introduction, TMS320 family overview 1-2
IR (instruction register), definition D-7
ISR (interrupt service routine), definition D-7
ISR code, sample 2-22
L
LAM (local acceptance mask) 10-16
LAMn_H (local acceptance mask register n (0,1)
high word) 10-17
latch phase of CPU cycle D-8
LAMn_L (local acceptance mask register n (0,1) low
word) 10-17
local data memory 3-12
off-chip 3-15
on-chip 3-15
logic phase of CPU cycle D-8
low power modes 4-3
M
MCR (master control register), figure 10-22
MDER (mailbox direction enable register) 10-18
memory 3-1
address map, data page 0 3-14
buses 3-3
configuration
global data memory 3-15
local data 3-15
off-chip local data memory 3-15
on-chip local data memory 3-15
factory masked on–chip ROM 3-2
flash 3-2
flash control register access 3-2
global data memory 3-15
address generation 3-16
local data 3-12 to 3-15
’X24x peripheral memory map 3-13
on-chip, advantages 3-3
organization 3-3
’X24x peripheral memory map 3-13
I/O space address map for ’F243 3-16
local data memory pages 3-14
memory map for ’LC2402 3-9
memory map for ’LC2404 3-8
memory map for ’LC2406 3-7
memory map for ’LF2402 3-6
memory map for ’LF2406 3-5
memory map for ’LF2407 3-4
program memory configuration 3-10
program memory map for ’LF2407 3-10
program 3-10 to 3-11
segments 3-3
total address range 3-1
MSGCTRLn (CAN message control field),
figure 10-11
MSGIDnH (message identifier for high word mail-
boxes 0–5), figure 10-10
MSGIDnL (message identifier for low word mail-
boxes 0–5), figure 10-11
N
next program address register (NPAR), defini-
tion D-10
nonmaskable interrupts 2-18
NPAR (next program address register), defini-
tion D-10
O
OCRA, I/O mux control register A 5-5
OCRB
configuration table, for ’F241/3 only 5-7
I/O mux control register B 5-6